VU2 185.324 Compilation Techniques for VLIW Architectures

Dietmar Ebner and Florian Brandner SS2008 TUWIS++ Pages The course gives an overview of VLIW design principles and captures several real world examples along with their peculiarities compared to the general purpose computing domain. The main focus is on compilation techniques for ILP compilers, in particular speculation and predication, region scheduling techniques and software pipelining.

Date/Time

• Mi, 5.3.2008 13:00 - 14:30 s.t. Seminarraum 1/3 OPG: Combined introduction to all courses at the institute.
• Regular Meetings are on Tuesdays from 16:00 to 18:00 at the Library of the Institute for Computer Languages, Argentinierstr. 8, 1040 Wien, 4. Stk
   
  Preliminary Appointments: 11.3, 1.4, 8.4, 15.4, 22.4, 29.4, 6.5, 20.5, 27.5, 3.6

Slides

11.03.2008	Introduction to Emedded Systems and VLIW
01.04.2008	VLIW Principles, Instruction Set Design, and Instruction Encoding
08.04.2008	VLIW Architecture and Microarchitecture, Example Architectures
15.04.2008	Floating Point Arithmetic, Embedded C, Compiling for VLIWs, Loop Unrolling
22.04.2008	The VEX compiler toolchain sorry - no downloads this time; drop us a mail if you want a copy of the slides.	-
29.04.2008	Highlevel optimizations, Scalar optimizations, Loop optimizations
06.05.2008	Code Layout Techniques, Code Generation, Dependence Testing
20.05.2008	List Scheduling, Resource Models, Trace Scheduling
27.05.2008	Super-/Hyperblock, Treegions, Region Enlargement Techniques
03.06.2008	Cyclic Scheduling, Modulo Scheduling, If-conversion

Contents

• Overview of Embedded Systems
  Introduction; characterization and classification; application areas;
• Introduction to VLIW architectures
  historical retrospective; design philosophy; ISA design; instruction set encoding; typical instruction set extensions; clustered architectures; comparison with superscalar design principles;
• Example Architectures:
  MultiFlow TRACE; TI C62xx; ST2xx, VEX, CHILI, IA64
• The Role of the Compiler:
  compiling for ILP; structure of an ILP compiler; language extensions for embedded systems; retargetability; profiling techniques; power-aware compilation
• The VEX toolchain:
introduction to the VEX compiler and simulator
• High Level Optimizations:
  loop transformations; inlining; alias analysis; cache optimizations
• Code Generation and Code Layout
  code generation techniques; DAG-based approaches
• Scheduling Techniques:
  region scheduling (trace-/superblock-/hyperblock scheduling); software pipelining; phase-ordering problems
• Predication/Speculation:
  predicated execution models; if-conversion; speculative execution; integrated techniques

Assignments

15.04.2008-22.04.2008	Assignments covering lectures 1-4
22.04.2008-27.05.2008	Assignment 2 Click here to download the benchmarks and the assembler parser template. We encountered a small error* in the makefile, please download the corrected file here and replace the original one.

Practical assignments will use the VEX simulation/compilation system freely available at:

http://www.hpl.hp.com/downloads/vex

* An option (-r) causes the decoder to use a floating point based DCT implementation. Please download the new makefile and invoke the following commands:

make clean
make
make gen

Grading

Assignments and oral exam.

Exam	50 points
Assignment sheet 1	20 points
Assignment sheet 2	30 points

Literature

Fisher, Faraboschi, Young
Embedded Computing
A VLIW Approach to Architecture, Compilers and Tools
http://www.vliw.org/book
ISBN: 1-55860-766-8

The book is available at the library.

Contact

Dietmar Ebner
http://www.complang.tuwien.ac.at/cd/ebner/

Florian Brandner
http://www.complang.tuwien.ac.at/cd/brandner/