/*
 * Copyright (c) 1997-1999 Massachusetts Institute of Technology
 * Copyright (c) 2000-2002 Stefan Kral
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

/* This file was automatically generated --- DO NOT EDIT */
/* Generated on Tue Feb 19 14:30:23 CET 2002 */

#include <fftw-int.h>
#include <fftw.h>



DECLARE_SIMD_CONST2 (PK500000000PK500000000, +0.5000000000000000000000000,
		     +0.5000000000000000000000000);
DECLARE_SIMD_CONST2 (PK866025403PK866025403, +0.8660254037844386467637232,
		     +0.8660254037844386467637232);
DECLARE_SIMD_CONST2 (PK250000000PK250000000, +0.2500000000000000000000000,
		     +0.2500000000000000000000000);
DECLARE_SIMD_CONST2 (PK1_618033988PK1_618033988, +1.6180339887498948482045868,
		     +1.6180339887498948482045868);
DECLARE_SIMD_CONST2 (PK559016994PK559016994, +0.5590169943749474241022934,
		     +0.5590169943749474241022934);
DECLARE_SIMD_CONST2 (PK587785252PK587785252, +0.5877852522924731291687060,
		     +0.5877852522924731291687060);

void
fftwi_no_twiddle_15 (const fftw_complex * inC, fftw_complex * outC,
		     int istride, int ostride)
{
     const fftw_simd2 *input = (const fftw_simd2 *) inC;
     fftw_simd2 *output = (fftw_simd2 *) outC;
     DECLARE_SIMD_TMPVAR2 (t1006);
     DECLARE_SIMD_TMPVAR2 (t1005);
     DECLARE_SIMD_TMPVAR2 (t1004);
     DECLARE_SIMD_TMPVAR2 (t1037);
     DECLARE_SIMD_TMPVAR2 (t1003);
     DECLARE_SIMD_TMPVAR2 (t1001);
     DECLARE_SIMD_TMPVAR2 (t1032);
     DECLARE_SIMD_TMPVAR2 (t1038);
     DECLARE_SIMD_TMPVAR2 (t1030);
     DECLARE_SIMD_TMPVAR2 (t1074);
     DECLARE_SIMD_TMPVAR2 (t1014);
     DECLARE_SIMD_TMPVAR2 (t1013);
     DECLARE_SIMD_TMPVAR2 (t1012);
     DECLARE_SIMD_TMPVAR2 (t1048);
     DECLARE_SIMD_TMPVAR2 (t1011);
     DECLARE_SIMD_TMPVAR2 (t1043);
     DECLARE_SIMD_TMPVAR2 (t1009);
     DECLARE_SIMD_TMPVAR2 (t1028);
     DECLARE_SIMD_TMPVAR2 (t1027);
     DECLARE_SIMD_TMPVAR2 (t1026);
     DECLARE_SIMD_TMPVAR2 (t1071);
     DECLARE_SIMD_TMPVAR2 (t1025);
     DECLARE_SIMD_TMPVAR2 (t1066);
     DECLARE_SIMD_TMPVAR2 (t1020);
     DECLARE_SIMD_TMPVAR2 (t1018);
     DECLARE_SIMD_TMPVAR2 (t1017);
     DECLARE_SIMD_TMPVAR2 (t1016);
     DECLARE_SIMD_TMPVAR2 (t1055);
     DECLARE_SIMD_TMPVAR2 (t1015);
     DECLARE_SIMD_TMPVAR2 (t1050);
     DECLARE_SIMD_TMPVAR2 (t1010);
     DECLARE_SIMD_TMPVAR2 (t1024);
     DECLARE_SIMD_TMPVAR2 (t1023);
     DECLARE_SIMD_TMPVAR2 (t1022);
     DECLARE_SIMD_TMPVAR2 (t1064);
     DECLARE_SIMD_TMPVAR2 (t1021);
     DECLARE_SIMD_TMPVAR2 (t1059);
     DECLARE_SIMD_TMPVAR2 (t1019);
     DECLARE_SIMD_TMPVAR2 (t1094);
     DECLARE_SIMD_TMPVAR2 (t1007);
     DECLARE_SIMD_TMPVAR2 (t1097);
     DECLARE_SIMD_TMPVAR2 (t1008);
     DECLARE_SIMD_TMPVAR2 (t1002);
     DECLARE_SIMD_TMPVAR2 (t1089);
     DECLARE_SIMD_TMPVAR2 (t1056);
     DECLARE_SIMD_TMPVAR2 (t1079);
     DECLARE_SIMD_TMPVAR2 (t1042);
     DECLARE_SIMD_TMPVAR2 (t1049);
     DECLARE_SIMD_TMPVAR2 (t1078);
     DECLARE_SIMD_TMPVAR2 (t1041);
     DECLARE_SIMD_TMPVAR2 (t1076);
     DECLARE_SIMD_TMPVAR2 (t1120);
     DECLARE_SIMD_TMPVAR2 (t1039);
     DECLARE_SIMD_TMPVAR2 (t1146);
     DECLARE_SIMD_TMPVAR2 (t1072);
     DECLARE_SIMD_TMPVAR2 (t1081);
     DECLARE_SIMD_TMPVAR2 (t1058);
     DECLARE_SIMD_TMPVAR2 (t1065);
     DECLARE_SIMD_TMPVAR2 (t1080);
     DECLARE_SIMD_TMPVAR2 (t1057);
     DECLARE_SIMD_TMPVAR2 (t1077);
     DECLARE_SIMD_TMPVAR2 (t1123);
     DECLARE_SIMD_TMPVAR2 (t1040);
     DECLARE_SIMD_TMPVAR2 (t1149);
     DECLARE_SIMD_TMPVAR2 (t1000);
     DECLARE_SIMD_TMPVAR2 (t1086);
     DECLARE_SIMD_TMPVAR2 (t1207);
     DECLARE_SIMD_TMPVAR2 (t1208);
     DECLARE_SIMD_TMPVAR2 (t1101);
     DECLARE_SIMD_TMPVAR2 (t1083);
     DECLARE_SIMD_TMPVAR2 (t1160);
     DECLARE_SIMD_TMPVAR2 (t1106);
     DECLARE_SIMD_TMPVAR2 (t1100);
     DECLARE_SIMD_TMPVAR2 (t1190);
     DECLARE_SIMD_TMPVAR2 (t1098);
     DECLARE_SIMD_TMPVAR2 (t1082);
     DECLARE_SIMD_TMPVAR2 (t1205);
     DECLARE_SIMD_TMPVAR2 (t1210);
     DECLARE_SIMD_TMPVAR2 (t1141);
     DECLARE_SIMD_TMPVAR2 (t1031);
     DECLARE_SIMD_TMPVAR2 (t1138);
     DECLARE_SIMD_TMPVAR2 (t1029);
     DECLARE_SIMD_TMPVAR2 (t1135);
     DECLARE_SIMD_TMPVAR2 (t1153);
     DECLARE_SIMD_TMPVAR2 (t1162);
     DECLARE_SIMD_TMPVAR2 (t1158);
     DECLARE_SIMD_TMPVAR2 (t1152);
     DECLARE_SIMD_TMPVAR2 (t1203);
     DECLARE_SIMD_TMPVAR2 (t1134);
     DECLARE_SIMD_TMPVAR2 (t1150);
     DECLARE_SIMD_TMPVAR2 (t1206);
     DECLARE_SIMD_TMPVAR2 (t1209);
     DECLARE_SIMD_TMPVAR2 (t1115);
     DECLARE_SIMD_TMPVAR2 (t1075);
     DECLARE_SIMD_TMPVAR2 (t1112);
     DECLARE_SIMD_TMPVAR2 (t1073);
     DECLARE_SIMD_TMPVAR2 (t1109);
     DECLARE_SIMD_TMPVAR2 (t1127);
     DECLARE_SIMD_TMPVAR2 (t1161);
     DECLARE_SIMD_TMPVAR2 (t1132);
     DECLARE_SIMD_TMPVAR2 (t1126);
     DECLARE_SIMD_TMPVAR2 (t1196);
     DECLARE_SIMD_TMPVAR2 (t1108);
     DECLARE_SIMD_TMPVAR2 (t1124);

     simd_ld2 (input[istride * 10], t1006);
     simd_ld2 (input[istride * 5], t1005);
     simd_add2 (t1005, t1006, t1004);
     simd_sub2 (t1006, t1005, t1037);
     simd_ld2 (input[0], t1003);
     simd_add2 (t1003, t1004, t1001);
     simd_fnmca2 (PK500000000PK500000000, t1004, t1003, t1032);
     simd_swapchsH2 (t1037, t1038);
     simd_fmca2 (PK866025403PK866025403, t1038, t1032, t1030);
     simd_fnmca2 (PK866025403PK866025403, t1038, t1032, t1074);
     simd_ld2 (input[istride * 13], t1014);
     simd_ld2 (input[istride * 8], t1013);
     simd_add2 (t1013, t1014, t1012);
     simd_sub2 (t1014, t1013, t1048);
     simd_ld2 (input[istride * 3], t1011);
     simd_fnmca2 (PK500000000PK500000000, t1012, t1011, t1043);
     simd_add2 (t1011, t1012, t1009);
     simd_ld2 (input[istride * 4], t1028);
     simd_ld2 (input[istride * 14], t1027);
     simd_add2 (t1027, t1028, t1026);
     simd_sub2 (t1028, t1027, t1071);
     simd_ld2 (input[istride * 9], t1025);
     simd_fnmca2 (PK500000000PK500000000, t1026, t1025, t1066);
     simd_add2 (t1025, t1026, t1020);
     simd_ld2 (input[istride * 7], t1018);
     simd_ld2 (input[istride * 2], t1017);
     simd_add2 (t1017, t1018, t1016);
     simd_sub2 (t1018, t1017, t1055);
     simd_ld2 (input[istride * 12], t1015);
     simd_fnmca2 (PK500000000PK500000000, t1016, t1015, t1050);
     simd_add2 (t1015, t1016, t1010);
     simd_ld2 (input[istride], t1024);
     simd_ld2 (input[istride * 11], t1023);
     simd_add2 (t1023, t1024, t1022);
     simd_sub2 (t1024, t1023, t1064);
     simd_ld2 (input[istride * 6], t1021);
     simd_fnmca2 (PK500000000PK500000000, t1022, t1021, t1059);
     simd_add2 (t1021, t1022, t1019);
     simd_sub2 (t1009, t1010, t1094);
     simd_add2 (t1009, t1010, t1007);
     simd_sub2 (t1019, t1020, t1097);
     simd_add2 (t1019, t1020, t1008);
     simd_add2 (t1007, t1008, t1002);
     simd_sub2 (t1007, t1008, t1089);
     simd_swapchsH2 (t1055, t1056);
     simd_fnmca2 (PK866025403PK866025403, t1056, t1050, t1079);
     simd_fmca2 (PK866025403PK866025403, t1056, t1050, t1042);
     simd_swapchsH2 (t1048, t1049);
     simd_fnmca2 (PK866025403PK866025403, t1049, t1043, t1078);
     simd_fmca2 (PK866025403PK866025403, t1049, t1043, t1041);
     simd_add2 (t1078, t1079, t1076);
     simd_sub2 (t1078, t1079, t1120);
     simd_add2 (t1041, t1042, t1039);
     simd_sub2 (t1041, t1042, t1146);
     simd_swapchsH2 (t1071, t1072);
     simd_fnmca2 (PK866025403PK866025403, t1072, t1066, t1081);
     simd_fmca2 (PK866025403PK866025403, t1072, t1066, t1058);
     simd_swapchsH2 (t1064, t1065);
     simd_fnmca2 (PK866025403PK866025403, t1065, t1059, t1080);
     simd_fmca2 (PK866025403PK866025403, t1065, t1059, t1057);
     simd_add2 (t1080, t1081, t1077);
     simd_sub2 (t1080, t1081, t1123);
     simd_add2 (t1057, t1058, t1040);
     simd_sub2 (t1057, t1058, t1149);
     simd_add2 (t1001, t1002, t1000);
     simd_fnmca2 (PK250000000PK250000000, t1002, t1001, t1086);
     simd_st2 (t1000, output[0]);
     simd_fmca2 (PK1_618033988PK1_618033988, t1094, t1097, t1207);
     simd_fnmca2 (PK1_618033988PK1_618033988, t1097, t1094, t1208);
     simd_fmca2 (PK559016994PK559016994, t1089, t1086, t1101);
     simd_fnmca2 (PK559016994PK559016994, t1089, t1086, t1083);
     simd_swapchsH2 (t1207, t1160);
     simd_fmca2 (PK587785252PK587785252, t1160, t1101, t1106);
     simd_fnmca2 (PK587785252PK587785252, t1160, t1101, t1100);
     simd_st2 (t1106, output[ostride * 9]);
     simd_st2 (t1100, output[ostride * 6]);
     simd_swapchsH2 (t1208, t1190);
     simd_fmca2 (PK587785252PK587785252, t1190, t1083, t1098);
     simd_fnmca2 (PK587785252PK587785252, t1190, t1083, t1082);
     simd_st2 (t1098, output[ostride * 3]);
     simd_st2 (t1082, output[ostride * 12]);
     simd_fmca2 (PK1_618033988PK1_618033988, t1146, t1149, t1205);
     simd_fnmca2 (PK1_618033988PK1_618033988, t1149, t1146, t1210);
     simd_sub2 (t1039, t1040, t1141);
     simd_add2 (t1039, t1040, t1031);
     simd_fnmca2 (PK250000000PK250000000, t1031, t1030, t1138);
     simd_add2 (t1030, t1031, t1029);
     simd_st2 (t1029, output[ostride * 10]);
     simd_fnmca2 (PK559016994PK559016994, t1141, t1138, t1135);
     simd_fmca2 (PK559016994PK559016994, t1141, t1138, t1153);
     simd_swapchsH2 (t1205, t1162);
     simd_fnmca2 (PK587785252PK587785252, t1162, t1153, t1158);
     simd_fmca2 (PK587785252PK587785252, t1162, t1153, t1152);
     simd_st2 (t1158, output[ostride]);
     simd_st2 (t1152, output[ostride * 4]);
     simd_swapchsH2 (t1210, t1203);
     simd_fmca2 (PK587785252PK587785252, t1203, t1135, t1134);
     simd_fnmca2 (PK587785252PK587785252, t1203, t1135, t1150);
     simd_st2 (t1134, output[ostride * 13]);
     simd_st2 (t1150, output[ostride * 7]);
     simd_fmca2 (PK1_618033988PK1_618033988, t1120, t1123, t1206);
     simd_fnmca2 (PK1_618033988PK1_618033988, t1123, t1120, t1209);
     simd_sub2 (t1076, t1077, t1115);
     simd_add2 (t1076, t1077, t1075);
     simd_fnmca2 (PK250000000PK250000000, t1075, t1074, t1112);
     simd_add2 (t1074, t1075, t1073);
     simd_st2 (t1073, output[ostride * 5]);
     simd_fnmca2 (PK559016994PK559016994, t1115, t1112, t1109);
     simd_fmca2 (PK559016994PK559016994, t1115, t1112, t1127);
     simd_swapchsH2 (t1206, t1161);
     simd_fnmca2 (PK587785252PK587785252, t1161, t1127, t1132);
     simd_fmca2 (PK587785252PK587785252, t1161, t1127, t1126);
     simd_st2 (t1132, output[ostride * 11]);
     simd_st2 (t1126, output[ostride * 14]);
     simd_swapchsH2 (t1209, t1196);
     simd_fmca2 (PK587785252PK587785252, t1196, t1109, t1108);
     simd_fnmca2 (PK587785252PK587785252, t1196, t1109, t1124);
     simd_st2 (t1108, output[ostride * 8]);
     simd_st2 (t1124, output[ostride * 2]);
}


fftw_codelet_desc fftwi_no_twiddle_15_desc = {
     "fftwi_no_twiddle_15",
     (void (*)()) fftwi_no_twiddle_15,
     15,
     FFTW_BACKWARD,
     FFTW_NOTW,
     342,
     0,
     (const int *) 0,
};
