type vsimdreg = V_SimdReg of int
val makeNewVsimdreg : unit -> vsimdreg
module VSimdRegSet :
  sig
    type elt = vsimdreg
    and t
    val empty : t
    val is_empty : t -> bool
    val mem : elt -> t -> bool
    val add : elt -> t -> t
    val singleton : elt -> t
    val remove : elt -> t -> t
    val union : t -> t -> t
    val inter : t -> t -> t
    val diff : t -> t -> t
    val compare : t -> t -> int
    val equal : t -> t -> bool
    val subset : t -> t -> bool
    val iter : (elt -> unit) -> t -> unit
    val fold : (elt -> 'a -> 'a) -> t -> 'a -> 'a
    val for_all : (elt -> bool) -> t -> bool
    val exists : (elt -> bool) -> t -> bool
    val filter : (elt -> bool) -> t -> t
    val partition : (elt -> bool) -> t -> t * t
    val cardinal : t -> int
    val elements : t -> elt list
    val min_elt : t -> elt
    val max_elt : t -> elt
    val choose : t -> elt
  end
module VSimdRegMap :
  sig
    type key = vsimdreg
    and +'a t
    val empty : 'a t
    val add : key -> 'a -> 'a t -> 'a t
    val find : key -> 'a t -> 'a
    val remove : key -> 'a t -> 'a t
    val mem : key -> 'a t -> bool
    val iter : (key -> 'a -> unit) -> 'a t -> unit
    val map : ('a -> 'b) -> 'a t -> 'b t
    val mapi : (key -> 'a -> 'b) -> 'a t -> 'b t
    val fold : (key -> 'a -> 'b -> 'b) -> 'a t -> 'b -> 'b
  end
val vsimdregmap_find : VSimdRegMap.key -> 'a VSimdRegMap.t -> 'a option
val vsimdregmap_findE : VSimdRegMap.key -> 'a list VSimdRegMap.t -> 'a list
val vsimdregmap_addE :
  VSimdRegMap.key -> 'a -> 'a list VSimdRegMap.t -> 'a list VSimdRegMap.t
val vsimdregmap_addE' :
  'a -> VSimdRegMap.key -> 'a list VSimdRegMap.t -> 'a list VSimdRegMap.t
val vsimdregmap_cutE :
  VSimdRegMap.key -> 'a list VSimdRegMap.t -> 'a list VSimdRegMap.t
type vsign = V_Pos | V_Neg
and vsimdchspos = V_ChsLo | V_ChsHi | V_ChsLoHi
and vsimdpos = V_Lo | V_Hi
and realimag = RealPart | ImagPart
val vsimdchsposToConstants : vsimdchspos -> Number.number * Number.number
type vsimdinstroperand =
    V_SimdTmp of int
  | V_SimdDVar of VFpBasics.vfpaccess * Variable.array * int
  | V_SimdQVar of Variable.array * int
  | V_SimdNConst of string
  | V_SimdNumConst of float * float
module VSimdInstrOperandSet :
  sig
    type elt = vsimdinstroperand
    and t
    val empty : t
    val is_empty : t -> bool
    val mem : elt -> t -> bool
    val add : elt -> t -> t
    val singleton : elt -> t
    val remove : elt -> t -> t
    val union : t -> t -> t
    val inter : t -> t -> t
    val diff : t -> t -> t
    val compare : t -> t -> int
    val equal : t -> t -> bool
    val subset : t -> t -> bool
    val iter : (elt -> unit) -> t -> unit
    val fold : (elt -> 'a -> 'a) -> t -> 'a -> 'a
    val for_all : (elt -> bool) -> t -> bool
    val exists : (elt -> bool) -> t -> bool
    val filter : (elt -> bool) -> t -> t
    val partition : (elt -> bool) -> t -> t * t
    val cardinal : t -> int
    val elements : t -> elt list
    val min_elt : t -> elt
    val max_elt : t -> elt
    val choose : t -> elt
  end
type vsimdrawvar =
    V_SimdRawQVar of int
  | V_SimdRawDVar of VFpBasics.vfpaccess * int
module VSimdRawVarSet :
  sig
    type elt = vsimdrawvar
    and t
    val empty : t
    val is_empty : t -> bool
    val mem : elt -> t -> bool
    val add : elt -> t -> t
    val singleton : elt -> t
    val remove : elt -> t -> t
    val union : t -> t -> t
    val inter : t -> t -> t
    val diff : t -> t -> t
    val compare : t -> t -> int
    val equal : t -> t -> bool
    val subset : t -> t -> bool
    val iter : (elt -> unit) -> t -> unit
    val fold : (elt -> 'a -> 'a) -> t -> 'a -> 'a
    val for_all : (elt -> bool) -> t -> bool
    val exists : (elt -> bool) -> t -> bool
    val filter : (elt -> bool) -> t -> t
    val partition : (elt -> bool) -> t -> t * t
    val cardinal : t -> int
    val elements : t -> elt list
    val min_elt : t -> elt
    val max_elt : t -> elt
    val choose : t -> elt
  end
val vsimdinstroperand_is_temporary : vsimdinstroperand -> bool
val vsimdinstroperand_is_twiddle : vsimdinstroperand -> bool
type vsimdternaryop = V_FMA2 | V_FMS2
and vsimdbinaryop =
    V_Add2
  | V_Sub2
  | V_Mul2
  | V_Acc2 of vsign * vsign
  | V_FNMcA2 of Number.number * Number.number
  | V_FMcA2 of Number.number * Number.number
  | V_FMcS2 of Number.number * Number.number
  | V_UnpackL
  | V_UnpackH
  | V_UnpackLH
and vsimdunaryop =
    V_Id
  | V_Swap
  | V_SwapChsL
  | V_SwapChsH
  | V_Chs of vsimdchspos
  | V_MulConst of Number.number * Number.number
val eq_vsimdunaryop : vsimdunaryop -> vsimdunaryop -> bool
val eq_vsimdbinaryop : vsimdbinaryop -> vsimdbinaryop -> bool
val vsimdbinopIsParallel : vsimdbinaryop -> bool
type vsimdinstr =
    V_SimdLoad2 of Variable.array * int * vsimdreg
  | V_SimdStore2 of vsimdreg * Variable.array * int
  | V_SimdUnaryOp of vsimdunaryop * vsimdreg * vsimdreg
  | V_SimdBinaryOp of vsimdbinaryop * vsimdreg * vsimdreg * vsimdreg
  | V_SimdTernaryOp of vsimdternaryop * vsimdreg * vsimdreg * vsimdreg *
      vsimdreg
val vsimdinstrToSrcregs : vsimdinstr -> vsimdreg list
val vsimdinstrToDstreg : vsimdinstr -> vsimdreg option
val vsimdinstrToReads : vsimdinstr -> vsimdreg list
val vsimdinstrToWrites : vsimdinstr -> vsimdreg list
val vsimdinstrToReadswritespair : vsimdinstr -> vsimdreg list * vsimdreg list
val vsimdinstrIsLoad : vsimdinstr -> bool
val vsimdinstrIsStore : vsimdinstr -> bool
val vsimdchsposToSwapped : vsimdchspos -> vsimdchspos
val vsimdchsposToSrcoperand : vsimdchspos -> vsimdinstroperand
val vsimdunaryopToSrcoperands : vsimdunaryop -> vsimdinstroperand list
val vsimdinstrToSrcoperands : vsimdinstr -> vsimdinstroperand list
val vsimdinstrToSrcrawvars : vsimdinstr -> vsimdrawvar list
val vsimdinstrToDstoperands : vsimdinstr -> vsimdinstroperand list
val vsimdunaryopToConst :
  vsimdunaryop -> (Number.number * Number.number) option
val vsimdbinaryopToConst :
  vsimdbinaryop -> (Number.number * Number.number) option
val vsimdinstrToConst : vsimdinstr -> (Number.number * Number.number) option
val vsimdinstrsToConsts :
  vsimdinstr list -> (Number.number * Number.number) list
val vsimdinstrsToDstregs : vsimdinstr list -> vsimdreg list
