/*
 * Copyright (c) 1997-1999 Massachusetts Institute of Technology
 * Copyright (c) 2000-2002 Stefan Kral
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

/* This file was automatically generated --- DO NOT EDIT */
/* Generated on Tue Feb 19 14:30:26 CET 2002 */

#include <fftw-int.h>
#include <fftw.h>



DECLARE_SIMD_CONST2 (PK1_000000000NK1_000000000, +1.0000000000000000000000000,
		     -1.0000000000000000000000000);
DECLARE_SIMD_CONST2 (PK707106781PK707106781, +0.7071067811865475244008444,
		     +0.7071067811865475244008444);
DECLARE_SIMD_CONST2 (PK2_414213562NK2_414213562, +2.4142135623730950488016887,
		     -2.4142135623730950488016887);
DECLARE_SIMD_CONST2 (PK414213562NK414213562, +0.4142135623730950488016887,
		     -0.4142135623730950488016887);
DECLARE_SIMD_CONST2 (PK923879532PK923879532, +0.9238795325112867561281832,
		     +0.9238795325112867561281832);
DECLARE_SIMD_CONST2 (PK707106781NK707106781, +0.7071067811865475244008444,
		     -0.7071067811865475244008444);
DECLARE_SIMD_CONST2 (PK382683432PK382683432, +0.3826834323650897717284600,
		     +0.3826834323650897717284600);

void
fftwi_no_twiddle_16 (const fftw_complex * inC, fftw_complex * outC,
		     int istride, int ostride)
{
     const fftw_simd2 *input = (const fftw_simd2 *) inC;
     fftw_simd2 *output = (fftw_simd2 *) outC;
     DECLARE_SIMD_TMPVAR2 (t1008);
     DECLARE_SIMD_TMPVAR2 (t1007);
     DECLARE_SIMD_TMPVAR2 (t1005);
     DECLARE_SIMD_TMPVAR2 (t1049);
     DECLARE_SIMD_TMPVAR2 (t1010);
     DECLARE_SIMD_TMPVAR2 (t1009);
     DECLARE_SIMD_TMPVAR2 (t1006);
     DECLARE_SIMD_TMPVAR2 (t1053);
     DECLARE_SIMD_TMPVAR2 (t1003);
     DECLARE_SIMD_TMPVAR2 (t1136);
     DECLARE_SIMD_TMPVAR2 (t1050);
     DECLARE_SIMD_TMPVAR2 (t1104);
     DECLARE_SIMD_TMPVAR2 (t1044);
     DECLARE_SIMD_TMPVAR2 (t1014);
     DECLARE_SIMD_TMPVAR2 (t1013);
     DECLARE_SIMD_TMPVAR2 (t1057);
     DECLARE_SIMD_TMPVAR2 (t1011);
     DECLARE_SIMD_TMPVAR2 (t1016);
     DECLARE_SIMD_TMPVAR2 (t1015);
     DECLARE_SIMD_TMPVAR2 (t1064);
     DECLARE_SIMD_TMPVAR2 (t1012);
     DECLARE_SIMD_TMPVAR2 (t1004);
     DECLARE_SIMD_TMPVAR2 (t1139);
     DECLARE_SIMD_TMPVAR2 (t1060);
     DECLARE_SIMD_TMPVAR2 (t1056);
     DECLARE_SIMD_TMPVAR2 (t1058);
     DECLARE_SIMD_TMPVAR2 (t1055);
     DECLARE_SIMD_TMPVAR2 (t1109);
     DECLARE_SIMD_TMPVAR2 (t1054);
     DECLARE_SIMD_TMPVAR2 (t1022);
     DECLARE_SIMD_TMPVAR2 (t1021);
     DECLARE_SIMD_TMPVAR2 (t1019);
     DECLARE_SIMD_TMPVAR2 (t1074);
     DECLARE_SIMD_TMPVAR2 (t1024);
     DECLARE_SIMD_TMPVAR2 (t1023);
     DECLARE_SIMD_TMPVAR2 (t1020);
     DECLARE_SIMD_TMPVAR2 (t1078);
     DECLARE_SIMD_TMPVAR2 (t1157);
     DECLARE_SIMD_TMPVAR2 (t1017);
     DECLARE_SIMD_TMPVAR2 (t1028);
     DECLARE_SIMD_TMPVAR2 (t1027);
     DECLARE_SIMD_TMPVAR2 (t1025);
     DECLARE_SIMD_TMPVAR2 (t1091);
     DECLARE_SIMD_TMPVAR2 (t1030);
     DECLARE_SIMD_TMPVAR2 (t1029);
     DECLARE_SIMD_TMPVAR2 (t1026);
     DECLARE_SIMD_TMPVAR2 (t1087);
     DECLARE_SIMD_TMPVAR2 (t1156);
     DECLARE_SIMD_TMPVAR2 (t1018);
     DECLARE_SIMD_TMPVAR2 (t1158);
     DECLARE_SIMD_TMPVAR2 (t1150);
     DECLARE_SIMD_TMPVAR2 (t1075);
     DECLARE_SIMD_TMPVAR2 (t1116);
     DECLARE_SIMD_TMPVAR2 (t1070);
     DECLARE_SIMD_TMPVAR2 (t1152);
     DECLARE_SIMD_TMPVAR2 (t1149);
     DECLARE_SIMD_TMPVAR2 (t1038);
     DECLARE_SIMD_TMPVAR2 (t1002);
     DECLARE_SIMD_TMPVAR2 (t1088);
     DECLARE_SIMD_TMPVAR2 (t1083);
     DECLARE_SIMD_TMPVAR2 (t1122);
     DECLARE_SIMD_TMPVAR2 (t1035);
     DECLARE_SIMD_TMPVAR2 (t1001);
     DECLARE_SIMD_TMPVAR2 (t1039);
     DECLARE_SIMD_TMPVAR2 (t1032);
     DECLARE_SIMD_TMPVAR2 (t1040);
     DECLARE_SIMD_TMPVAR2 (t1031);
     DECLARE_SIMD_TMPVAR2 (t1000);
     DECLARE_SIMD_TMPVAR2 (t1042);
     DECLARE_SIMD_TMPVAR2 (t1095);
     DECLARE_SIMD_TMPVAR2 (t1079);
     DECLARE_SIMD_TMPVAR2 (t1168);
     DECLARE_SIMD_TMPVAR2 (t1092);
     DECLARE_SIMD_TMPVAR2 (t1169);
     DECLARE_SIMD_TMPVAR2 (t1180);
     DECLARE_SIMD_TMPVAR2 (t1170);
     DECLARE_SIMD_TMPVAR2 (t1093);
     DECLARE_SIMD_TMPVAR2 (t1041);
     DECLARE_SIMD_TMPVAR2 (t1098);
     DECLARE_SIMD_TMPVAR2 (t1100);
     DECLARE_SIMD_TMPVAR2 (t1094);
     DECLARE_SIMD_TMPVAR2 (t1140);
     DECLARE_SIMD_TMPVAR2 (t1134);
     DECLARE_SIMD_TMPVAR2 (t1162);
     DECLARE_SIMD_TMPVAR2 (t1151);
     DECLARE_SIMD_TMPVAR2 (t1166);
     DECLARE_SIMD_TMPVAR2 (t1160);
     DECLARE_SIMD_TMPVAR2 (t1133);
     DECLARE_SIMD_TMPVAR2 (t1164);
     DECLARE_SIMD_TMPVAR2 (t1167);
     DECLARE_SIMD_TMPVAR2 (t1161);
     DECLARE_SIMD_TMPVAR2 (t1110);
     DECLARE_SIMD_TMPVAR2 (t1102);
     DECLARE_SIMD_TMPVAR2 (t1127);
     DECLARE_SIMD_TMPVAR2 (t1118);
     DECLARE_SIMD_TMPVAR2 (t1171);
     DECLARE_SIMD_TMPVAR2 (t1124);
     DECLARE_SIMD_TMPVAR2 (t1172);
     DECLARE_SIMD_TMPVAR2 (t1177);
     DECLARE_SIMD_TMPVAR2 (t1173);
     DECLARE_SIMD_TMPVAR2 (t1125);
     DECLARE_SIMD_TMPVAR2 (t1101);
     DECLARE_SIMD_TMPVAR2 (t1130);
     DECLARE_SIMD_TMPVAR2 (t1132);
     DECLARE_SIMD_TMPVAR2 (t1126);

     simd_ld2 (input[istride * 8], t1008);
     simd_ld2 (input[0], t1007);
     simd_add2 (t1007, t1008, t1005);
     simd_sub2 (t1007, t1008, t1049);
     simd_ld2 (input[istride * 12], t1010);
     simd_ld2 (input[istride * 4], t1009);
     simd_add2 (t1009, t1010, t1006);
     simd_sub2 (t1009, t1010, t1053);
     simd_add2 (t1005, t1006, t1003);
     simd_sub2 (t1005, t1006, t1136);
     simd_swapchsH2 (t1053, t1050);
     simd_add2 (t1050, t1049, t1104);
     simd_sub2 (t1049, t1050, t1044);
     simd_ld2 (input[istride * 10], t1014);
     simd_ld2 (input[istride * 2], t1013);
     simd_sub2 (t1013, t1014, t1057);
     simd_add2 (t1013, t1014, t1011);
     simd_ld2 (input[istride * 6], t1016);
     simd_ld2 (input[istride * 14], t1015);
     simd_sub2 (t1015, t1016, t1064);
     simd_add2 (t1015, t1016, t1012);
     simd_add2 (t1011, t1012, t1004);
     simd_sub2 (t1012, t1011, t1139);
     simd_swapchsH2 (t1064, t1060);
     simd_add2 (t1060, t1064, t1056);
     simd_swapchsH2 (t1057, t1058);
     simd_sub2 (t1057, t1058, t1055);
     simd_sub2 (t1056, t1055, t1109);
     simd_add2 (t1055, t1056, t1054);
     simd_ld2 (input[istride * 9], t1022);
     simd_ld2 (input[istride], t1021);
     simd_add2 (t1021, t1022, t1019);
     simd_sub2 (t1021, t1022, t1074);
     simd_ld2 (input[istride * 13], t1024);
     simd_ld2 (input[istride * 5], t1023);
     simd_add2 (t1023, t1024, t1020);
     simd_sub2 (t1023, t1024, t1078);
     simd_sub2 (t1019, t1020, t1157);
     simd_add2 (t1019, t1020, t1017);
     simd_ld2 (input[istride * 7], t1028);
     simd_ld2 (input[istride * 15], t1027);
     simd_add2 (t1027, t1028, t1025);
     simd_sub2 (t1027, t1028, t1091);
     simd_ld2 (input[istride * 11], t1030);
     simd_ld2 (input[istride * 3], t1029);
     simd_add2 (t1029, t1030, t1026);
     simd_sub2 (t1029, t1030, t1087);
     simd_sub2 (t1025, t1026, t1156);
     simd_add2 (t1025, t1026, t1018);
     simd_swap2 (t1157, t1158);
     simd_fmca2 (PK1_000000000NK1_000000000, t1157, t1158, t1150);
     simd_swapchsH2 (t1078, t1075);
     simd_add2 (t1075, t1074, t1116);
     simd_sub2 (t1074, t1075, t1070);
     simd_swap2 (t1156, t1152);
     simd_fnmca2 (PK1_000000000NK1_000000000, t1156, t1152, t1149);
     simd_sub2 (t1018, t1017, t1038);
     simd_add2 (t1017, t1018, t1002);
     simd_swap2 (t1091, t1088);
     simd_fmca2 (PK1_000000000NK1_000000000, t1087, t1088, t1083);
     simd_fnmca2 (PK1_000000000NK1_000000000, t1087, t1088, t1122);
     simd_sub2 (t1003, t1004, t1035);
     simd_add2 (t1003, t1004, t1001);
     simd_swapchsH2 (t1038, t1039);
     simd_add2 (t1039, t1035, t1032);
     simd_sub2 (t1035, t1039, t1040);
     simd_st2 (t1032, output[ostride * 4]);
     simd_st2 (t1040, output[ostride * 12]);
     simd_add2 (t1001, t1002, t1031);
     simd_sub2 (t1001, t1002, t1000);
     simd_st2 (t1031, output[0]);
     simd_st2 (t1000, output[ostride * 8]);
     simd_fmca2 (PK707106781PK707106781, t1054, t1044, t1042);
     simd_fnmca2 (PK707106781PK707106781, t1054, t1044, t1095);
     simd_swap2 (t1070, t1079);
     simd_fnmca2 (PK2_414213562NK2_414213562, t1070, t1079, t1168);
     simd_swap2 (t1083, t1092);
     simd_fmca2 (PK414213562NK414213562, t1083, t1092, t1169);
     simd_fmca2 (PK414213562NK414213562, t1168, t1169, t1180);
     simd_fnmca2 (PK414213562NK414213562, t1168, t1169, t1170);
     simd_fmca2 (PK923879532PK923879532, t1170, t1042, t1093);
     simd_fnmca2 (PK923879532PK923879532, t1170, t1042, t1041);
     simd_st2 (t1093, output[ostride]);
     simd_st2 (t1041, output[ostride * 9]);
     simd_swapchsH2 (t1180, t1098);
     simd_fmca2 (PK923879532PK923879532, t1098, t1095, t1100);
     simd_fnmca2 (PK923879532PK923879532, t1098, t1095, t1094);
     simd_st2 (t1100, output[ostride * 5]);
     simd_st2 (t1094, output[ostride * 13]);
     simd_swapchsH2 (t1139, t1140);
     simd_sub2 (t1136, t1140, t1134);
     simd_add2 (t1140, t1136, t1162);
     simd_sub2 (t1149, t1150, t1151);
     simd_add2 (t1150, t1149, t1166);
     simd_fmca2 (PK707106781NK707106781, t1151, t1134, t1160);
     simd_fnmca2 (PK707106781NK707106781, t1151, t1134, t1133);
     simd_st2 (t1160, output[ostride * 6]);
     simd_st2 (t1133, output[ostride * 14]);
     simd_swap2 (t1166, t1164);
     simd_fmca2 (PK707106781PK707106781, t1164, t1162, t1167);
     simd_fnmca2 (PK707106781PK707106781, t1164, t1162, t1161);
     simd_st2 (t1167, output[ostride * 2]);
     simd_st2 (t1161, output[ostride * 10]);
     simd_swapchsH2 (t1109, t1110);
     simd_fmca2 (PK707106781PK707106781, t1110, t1104, t1102);
     simd_fnmca2 (PK707106781PK707106781, t1110, t1104, t1127);
     simd_swap2 (t1116, t1118);
     simd_fnmca2 (PK414213562NK414213562, t1116, t1118, t1171);
     simd_swap2 (t1122, t1124);
     simd_fmca2 (PK2_414213562NK2_414213562, t1122, t1124, t1172);
     simd_fmca2 (PK2_414213562NK2_414213562, t1171, t1172, t1177);
     simd_fnmca2 (PK2_414213562NK2_414213562, t1171, t1172, t1173);
     simd_fmca2 (PK382683432PK382683432, t1173, t1102, t1125);
     simd_fnmca2 (PK382683432PK382683432, t1173, t1102, t1101);
     simd_st2 (t1125, output[ostride * 3]);
     simd_st2 (t1101, output[ostride * 11]);
     simd_swapchsH2 (t1177, t1130);
     simd_fmca2 (PK382683432PK382683432, t1130, t1127, t1132);
     simd_fnmca2 (PK382683432PK382683432, t1130, t1127, t1126);
     simd_st2 (t1132, output[ostride * 7]);
     simd_st2 (t1126, output[ostride * 15]);
}


fftw_codelet_desc fftwi_no_twiddle_16_desc = {
     "fftwi_no_twiddle_16",
     (void (*)()) fftwi_no_twiddle_16,
     16,
     FFTW_BACKWARD,
     FFTW_NOTW,
     364,
     0,
     (const int *) 0,
};
