Some event specifiers for perfex on the Pentium 4. Note that if you specify several events in one perfex run, you have to avoid collisions of counters (perfex checks this for you) and ESCRs (perfex does not check this). You specify the counter in part after the "@" (e.g., ...@...0C=counter 12). The ESCR is determined by the counter and the event (see the "other possible counters" column). If two counters use the same value in the ESCR, you can share the ESCR (see the trace cache deliver and non-deliver cycles below). CTR ESCR Specifier event other possible counters 13 CRU_ESCR2 0x0003b000/0x0c001e04@0x8000000D Branches 12,13,16:escr2 14,15,17:escr3 13 CRU_ESCR2 0x0003b000/0x0c001804@0x8000000D taken branches 12,13,16:escr2 14,15,17:escr3 15 CRU_ESCR3 0x0003b000/0x0c001404@0x8000000F mispredicted (?) branches 12,13,16:escr2 14,15,17:escr3 15 CRU_ESCR3 0x0003b000/0x0c001004@0x8000000F taken mispredicted brs. 12,13,16:escr2 14,15,17:escr3 14 CRU_ESCR1 0x00039000/0x06000204@0x8000000e mispredicted branches 12,13,16:escr0 14,15,17:escr1 12 CRU_ESCR0 0x00039000/0x04000204@0x8000000C Instructions 12,13,16:escr0 14,15,17:escr1 12 CRU_ESCR0 0x00ff9000/0x04000204@0x8000000C Cycles (with <15 insts) 12,13,16:escr0 14,15,17:escr1 6 TC_ESCR1 0x00033000/0x02000804@0x80000006 trace cache deliver cycles 4,5:escr0 6,7:escr1 7 TC_ESCR1 0x000f3000/0x02000804@0x80000007 trace cache non-deliver cyc 4,5:escr0 6,7:escr1 4 TC_ESCR0 0x00033000/0x02004004@0x80000004 trace cache building cycles 4,5:escr0 6,7:escr1 4 TC_ESCR0 0x00033000/0x02004804@0x80000004 trace cache build/deliver c 4,5:escr0 6,7:escr1 5 TC_ESCR0 0x000f3000/0x02004804@0x80000005 trace cache other cycles 4,5:escr0 6,7:escr1 0 BPU_ESCR0 0x00031000/0x06000204@0x80000000 trace cache misses 0,1:escr0 2,3:escr1 16 CRU_ESCR2 0x0003b000/0x04000204@0x80000010 machine clear 12,13,16:escr2 14,15,17:escr3 6 TBPU_ESCR1 0x00035000/0x0a002004@0x80000006 mispred indirect branches 4,5:escr0 6,7:escr1 5 TBPU_ESCR0 0x00035000/0x08002004@0x80000005 indirect branches 4,5:escr0 6,7:escr1 The following does not seem to work: 17 CRU_ESCR2 0x0003b000/0x04001004@0x80000011 mach clear from self-mod 12,13,16:escr2 14,15,17:escr3